IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
40
May 19, 2009
Figure 10. 0.5 UI Late Frame Sync Input Signal Timing
Figure 11. 1 UI Late Frame Sync Input Signal Timing
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
Bit
Register
Address (Hex)
OUT1_PECL_LVDS
DIFFERENTIAL_IN_OUT_OSCI_CNFG
0A
OUTn_PATH_SEL[3:0] (n = 1 or 2)
OUT1_FREQ_CNFG, OUT2_FREQ_CNFG
71, 6D
OUTn_DIVIDER[3:0] (n = 1 or 2)
IN_SONET_SDH
INPUT_MODE_CNFG
09
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
OUTn_INV (n = 1 or 2)
OUT1_INV_CNFG, OUT2_INV_CNFG
73, 72
8K_EN
FR_MFR_SYNC_CNFG
74
2K_EN
8K_INV
2K_INV
8K_PUL
2K_PUL
2K_8K_PUL_POSITION
SYNC_BYPASS
SYNC_MONITOR_CNFG
7C
SYNC_MON_LIMT[2:0]
SYNC_PHn[1:0] (n = 1, 2 or 3)
SYNC_PHASE_CNFG
7D
EX_SYNC_ALARM_MON
OPERATING_STS
52
EX_SYNC_ALARM 1
INTERRUPTS3_STS
0F
EX_SYNC_ALARM 2
INTERRUPTS3_ENABLE_CNFG
12