參數(shù)資料
型號： IDT82V3355TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 72/135頁
文件大?。?/td> 0K
描述： IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝： 1,250
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
41
May 19, 2009
3.14
INTERRUPT SUMMARY
The interrupt sources of the device are as follows:
T4 DPLL locking status change
Input clocks for T0 path validity change
T0 selected input clock fail
Input clocks for T4 path change to be no qualified input clock
available
T0 DPLL operating mode switch
External sync alarm
All of the above interrupt events are indicated by the corresponding
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output charac-
teristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
Interrupt events are cleared by writing a ‘1’ to the corresponding
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
In addition, the interrupt of T0 selected input clock fail can be
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
3.15
T0 AND T4 SUMMARY
The main features supported by the T0 path are as follows:
Phase lock alarm;
Forced or Automatic input clock selection/switch;
3 primary and 3 secondary, temporary DPLL operating modes,
switched automatically or under external control;
Automatic switch between starting, acquisition and locked band-
widths/damping factors;
Programmable DPLL bandwidths from 0.1 Hz to 560 Hz in 11
steps;
Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
Output phase and frequency offset limited;
Automatic Instantaneous, Automatic Slow Averaged, Automatic
Fast Averaged or Manual holdover frequency offset acquiring;
PBO to minimize output phase transients;
Programmable output phase offset;
Low jitter multiple clock outputs with programmable polarity;
Low jitter 2 kHz and 8 kHz frame sync signal outputs with pro-
grammable pulse width and polarity;
The main features supported by the T4 path are as follows:
Forced or Automatic input clock selection/switch;
Locking to T0 DPLL output;
3 DPLL operating modes, switched automatically or under exter-
nal control;
Programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560
Hz;
Programmable damping factor: 1.2, 2.5, 5, 10 and 20;
Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
Output phase and frequency offset limited;
Automatic Instantaneous holdover frequency offset;
Low jitter multiple clock outputs with programmable polarity.
Table 31: Related Bit / Register in Chapter 3.14
Bit
Register
Address (Hex)
HZ_EN
INTERRUPT_CNFG
0C
INT_POL
LOS_FLAG_TO_TDO
MON_SW_PBO_CNFG
0B
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