參數(shù)資料
型號: IDT82V3355TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 82/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
50
May 19, 2009
41
-
IN_FREQ_READ_CH[3:0]
42
IN_FREQ_VALUE[7:0]
44
-
IN2_CMOS
_FREQ_H
ARD_ALA
RM
IN2_CMOS
_NO_ACTI
VITY_ALA
RM
IN2_CMOS
_PH_LOC
K_ALARM
-
IN1_CMOS
_FREQ_H
ARD_ALA
RM
IN1_CMOS
_NO_ACTI
VITY_ALA
RM
IN1_CMOS
_PH_LOC
K_ALARM
45
-
IN2_DIFF_
FREQ_HA
RD_ALAR
M
IN2_DIFF_
NO_ACTIV
ITY_ALAR
M
IN2_DIFF_
PH_LOCK
_ALARM
-
IN1_DIFF_
FREQ_HA
RD_ALAR
M
IN1_DIFF_
NO_ACTIV
ITY_ALAR
M
IN1_DIFF_
PH_LOCK
_ALARM
47
---
--
IN3_CMOS
_FREQ_H
ARD_ALA
RM
IN3_CMOS
_NO_ACTI
VITY_ALA
RM
IN3_CMOS
_PH_LOC
K_ALARM
T0 / T4 DPLL Input Clock Selection Registers
4A
-
IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS
-
4B
---
----
IN3_CMOS
4E
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
4F
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
]
50
-
T0_INPUT_SEL[3:0]
51
-
T4_LOCK_
T0
T0_FOR_T
4
T4_TEST_
T0_PH
T4_INPUT_SEL[3:0]
T0 / T4 DPLL State Machine Control Registers
52
EX_SYNC
_ALARM_
MON
T4_DPLL_
LOCK
T0_DPLL_
SOFT_FRE
Q_ALARM
T4_DPLL_
SOFT_FRE
Q_ALRAM
T0_DPLL_
LOCK
T0_DPLL_OPERATING_MODE[2:0]
53
-
T0_OPERATING_MODE[2:0]
54
-
T4_OPERATING_MODE[2:0]
T0 / T4 DPLL & APLL Configuration Registers
55
T0_APLL_PATH[3:0]
T0_ETH_OBSAI_16E1_
16T1_SEL[1:0]
T0_12E1_24T1_E3_T3
_SEL[1:0]
56
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_START_BW[4:0]
57
T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
58
T0_DPLL_LOCKED_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0]
Table 35: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
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