參數(shù)資料
型號： IDT82V3355TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 54/135頁
文件大?。?/td> 0K
描述： IC PLL WAN SYNC ETH 64-TQFP
標準包裝： 1,250
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
25
May 19, 2009
3.7.3
PHASE LOCK ALARM (T0 ONLY)
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be cal-
culated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding
INn_CMOS_PH_LOCK_ALARM
bit
(n
=
1,
2
or
3)
/
INn_DIFF_PH_LOCK_ALARM bit (n = 1 or 2).
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
Be cleared when a ‘1’ is written to the corresponding
INn_CMOS_PH_LOCK_ALARM
/
INn_DIFF_PH_LOCK_
ALARM bit;
Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in second) which starts from when the
alarm is raised.
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
Note that no phase lock alarm is raised if the T4 selected input clock
can not be locked.
Table 13: Related Bit / Register in Chapter 3.7
Bit
Register
Address (Hex)
FAST_LOS_SW
PHASE_LOSS_FINE_LIMIT_CNFG
5B *
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
PHASE_LOSS_COARSE_LIMIT_CNFG
5A *
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
OPERATING_STS
52
T4_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
T4_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0]
DPLL_FREQ_SOFT_LIMIT_CNFG
65
FREQ_LIMT_PH_LOS
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
67, 66
T4_STS 1
INTERRUPTS3_STS
0F
T4_STS 2
INTERRUPTS3_ENABLE_CNFG
12
TIME_OUT_VALUE[5:0]
PHASE_ALARM_TIME_OUT_CNFG
08
MULTI_FACTOR[1:0]
INn_CMOS_PH_LOCK_ALARM (n = 1, 2, or 3)
IN1_IN2_CMOS_STS, IN3_CMOS_STS
44, 47
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
IN1_IN2_DIFF_STS
45
PH_ALARM_TIMEOUT
INPUT_MODE_CNFG
09
T4_T0_SEL
T4_T0_REG_SEL_CNFG
07
Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
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