參數(shù)資料
型號: IDT82V3355TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 75/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Microprocessor Interface
44
May 19, 2009
4
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The microprocessor interface supports Serial
mode only.
In a read operation, the active edge of SCLK is selected by CLKE.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
In a write operation, data on SDI will be clocked in on the rising edge
of SCLK.
Figure 14. Serial Read Timing Diagram (CLKE Asserted Low)
Figure 15. Serial Read Timing Diagram (CLKE Asserted High)
CS
SCLK
SDI
SDO
High-Z
D0
D1
D2
D3 D4
D5
D6
D7
tpw2
tpw1
tsu2
tsu1
th1
th2
td1
t
d2
R/W A0
A1
A2
A3
A4
A5
A6
CS
SCLK
SDI
SDO
High-Z
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
td1
td2
th2
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