參數(shù)資料
型號: IDTSSTE32882HLBAKG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘緩沖器/驅(qū)動器,多路復(fù)用器
PLL:
主要目的: 存儲器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 800-2597-6
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
22
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
DC Specifications - Voltage
The SSTE32882 parametric values are specified for the device default control word settings, unless otherwise stated. Note
that the RC10 setting does not affect any of the parametric values.
Symbol
Parameter
Signals
Min
Nom
Max
Unit
VDD
DC Supply voltage (1.5V Operation)
1.425
1.5
1.575
V
DC Supply voltage (1.35V Operation)
1.282
1.35
1.451
V
VREF
DC Reference voltage
0.50 x VDD
0.51 x VDD
V
VTT
DC Termination voltage
VREF – 40 mV
VREF
VREF + 40 mV
V
VIH(AC) AC HIGH-level input voltage (1.5V Operation,
DDR3-800/1066/1333)
Data inputs1
VREF + 175 mV
VDD + 0.4
V
AC HIGH-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
VREF + 150 mV
VDD + 0.4
V
AC HIGH-level input voltage (1.35V Operation,
DDR3L-800/1066/1333)
Data inputs1
VREF + 150 mV
VDD + 0.2
V
AC HIGH-level input voltage (1.35V Operation, DDR3L-1600) Data inputs1
VREF + 135 mV
VDD + 0.2
V
VIL(AC) AC LOW-level input voltage (1.5V Operation,
DDR3-800/1066/1333)
Data inputs1
–0.4
VREF – 175 mV
V
AC LOW-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
–0.4
VREF – 150 mV
V
AC LOW-level input voltage(1.35V Operation,
DDR3L-800/1066/1333)
Data inputs1
–0.2
VREF – 150 mV
V
AC LOW-level input voltage (1.35V Operation, DDR3L-1600)
Data inputs1
–0.2
VREF – 135 mV
V
VIH(DC) DC HIGH-level input voltage(1.5V Operation)
Data inputs1
VREF + 100 mV
VDD + 0.4
V
DC HIGH-level input voltage(1.35V Operation)
Data inputs1
VREF + 90 mV
VDD + 0.2
V
VIL(DC) DC LOW-level input voltage(1.5V Operation)
Data inputs1
–0.4
VREF – 100 mV
V
DC LOW-level input voltage(1.35V Operation)
Data inputs1
–0.2
VREF – 90 mV
V
VIH(CMO
S)
HIGH-level input voltage
CMOS inputs2
0.65 x VDD
VDD
V
VIL(CMO
S)
LOW-level input voltage
CMOS inputs2
0
0.35 x VDD
V
VIL
(Static)
Static LOW-level input voltage3
CK, CK,
-
0.35 x VDD
V
VIX(AC) Differential input crosspoint voltage range(1.5V Operation,
DDR3-800/1066/1333/1600)
CK, CK, FBIN, FBIN
0.5xVDD - 175
mV
0.5 x VDD
0.5xVDD + 175
mV
V
0.5xVDD - 200
mV4
0.5 x VDD
0.5xVDD + 200
mV4
V
Differential input crosspoint voltage range(1.35V Operation,
DDR3L-800/1066/1333/1600)
CK, CK, FBIN, FBIN
0.5xVDD - 150
mV
0.5 x VDD
0.5xVDD + 150
mV
V
0.5xVDD - 180
mV5
0.5 x VDD
0.5xVDD + 180
mV5
V
VID(AC) Differential input voltage6 (1.5V Operation,
DDR3-800/1066/1333)
CK, CK
350
VDD
mV
Differential input voltage6(1.5V Operation, DDR3-1600)
CK, CK
300
VDD
mV
Differential input voltage6(1.35V Operation,
DDR3-800/1066/1333)
CK, CK
300
VDD
mV
Differential input voltage6 (1.35V Operation, DDR3-1600)
CK, CK
270
VDD
mV
IOH
HIGH-level output current7
All outputs except
ERROUT
-11
mA
IOL
LOW-level output current7
All outputs except
ERROUT
11
–-
mA
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