參數(shù)資料
型號(hào)： IDTSSTE32882HLBAKG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 30/73頁(yè)
文件大?。?/td> 0K
描述： IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器
PLL： 是
主要目的： 存儲(chǔ)器，DDR3，RDIMM
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 5:60
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 1.282 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（13.5x8）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2597-6
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
36
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Initialization
The SSTE32882HLB can be powered-on at 1.5V or 1.35V. After the voltage transition, stable power is provided for a
minimum of 200 s with RESET asserted.
When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced
to VDD/2, therefore the reference voltage (VREF) is not required to be stable during reset. In addition, when RESET is low, all
control registers are restored to their default states. The QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs must drive low
during reset, and all other outputs must float. As long as the RESET input is pulled low the register is in low power state and
input termination is not present.
A certain period of time (tACT) before the RESET input is pulled high the reference voltage needs to be stable within
specification, the clock input signal must be stable, the register inputs DCS[n:0] must be pulled high to prevent any fortuitous
access to the control registers. Also, DCKE0 and DCKE1 inputs must be pulled low for the complete stabilization time (tSTAB).
After reset and after the stabilization time (tSTAB), the register must meet the input setup and hold specification before
accepting and transfering data from the register inputs to the register outputs. The RESET input must always be held at a valid
logic level once the input clock is present.
To ensure defined outputs from the register before a stable clock has been supplied, the register must enter the reset state during
power-up. It may leave this state only after a low to high transition on RESET while a stable clock signal is present on CK and
CK.
In the DDR3 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore,
no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs
will float quickly (except for QACKE0, QACKE1, QBCKE0 and QBCKE1, which are driven low), relative to the time to
disable the differential input receivers. The figure below shows the system timing of clock and data during the initialization
sequence.
Timing of clock and data during initialization sequence
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
4 QxCKEn, QxODTn, QxCSn are not included in this range.
CK(1)
VDD
DCKE[0:1]
RESET
DA/C(2)
DODT[0:1]
DCS0
DCS[n:1](4)
PLL lock 6
s
tACT = 8 cycles
tINIT = 200 s
Controller guarantees high logic
Controller guarantees valid logic
Controller guarantees low logic
Controller guarantees valid logic
Register proper function and timing starting from here
Register drives CKE low until ready to transfer input signals
QxCKE[0:1]
QxODT[0:1]
QxCS[n:0](4)
ERROUT
Step 0,1 Step 2
Step 3
Step 5
Step 6
Step 7
Step 4
QxA/C(3)
High or Low
Y[0:3](1)
Register guarantees low logic
Register guarantees high logic
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