- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9684 > IDTSSTE32882HLBAKG8 (IDT, Integrated Device Technology Inc)IC REGISTERING CLK DRIVER 176BGA PDF資料下載
參數(shù)資料
| 型號： | IDTSSTE32882HLBAKG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 41/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 800-2597-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
46
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
CLOCK STOPPED POWER DOWN MODE
To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882HLB supports a
Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (VIL(static)) or float (will eventually
settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and
enters low-power static and standby operation. The corresponding timing are shown in “Clock Stopped Power Down Entry and
Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT Off“. The register device will stop its PLL and
floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1, which must be kept driven LOW.
The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this state, the
DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be disabled.
Clock Stopped Power Down Mode Entry
To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power down
mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After holding CK and
CK LOW (VIL(static)) for at least one tCKEV, both CK and CK can be floated (because of the (10K-100K Ohm) pulldown
resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not being driven).The register is now in
Clock Stopped Power Down mode.
After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one tCKEV before it can float DCKEn. At this
point, all input receivers and input termination of the SSTE32882HLB are disabled. The only active input circuits are CK and
CK, which are required to detect the wake up request from the host.
Clock Stopped Power Down Mode Exit
To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be driven to
HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can apply a frequency
and phase accurate input clock signal. Within tACT after CK and CK resumed normal operation, the SSTE32882HLB outputs
start becoming a function of their corresponding inputs. The state of the DCS[n:0] inputs must not be changed before the end
of tSTAB. The input clock CK and CK must be stable for a time equal or greater than tSTAB before any access to the
SSTE32882HLB can takes place.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V28C15M100BF2 | CONVERTER MOD DC/DC 15V 100W |
| MS27497E16F8PA | CONN RCPT 8POS WALL MNT W/PINS |
| V28C15M100B2 | CONVERTER MOD DC/DC 15V 100W |
| VI-J5X-MX-F2 | CONVERTER MOD DC/DC 5.2V 75W |
| D38999/24WJ4PB | CONN RCPT 56POS JAM NUT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTSSTE32882HLBBKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTE32882KA1AKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTUB32866BHLF | 功能描述:IC BUFFER 25BIT CONF REG 96LFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。