參數(shù)資料
型號(hào): IDTSSTE32882HLBAKG8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 55/73頁(yè)
文件大小: 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 800-2597-6
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
59
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
The IBT control is also located in this control word, with two options of 100
or 150 which can be selected to adapt to
different system scenarios. At power-up, the SSTE32882HLB IBT defaults to 100
. The system controller can reprogram the
termination resistance to 150
by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE, DCSn, DODTn, DCKEn, and
PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs do not have IBT.
If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are tied
together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs except the DCSn
and DODTn inputs.
The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can be driven
with an earlier signal compared to output clock and control in order to compensate for the slower signal travel speed. This
timing applies at all supported frequencies.
Effective IBT Tolerance Requirement
Min
Max
Total Effective IBT Value Tolerance1
1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms
-10%
+10%
Mismatch Tolerance Between R-IBT-Up and R-IBT-Down
Max
Mismatch Tolerance Between R-IBT-Up
and R-IBT-Down1
1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%)
ABS(5%)
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