- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IOP480 I/O Processor|IOP 480 Design Notes PDF資料下載
參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說明 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 245K |
| 代理商： | IOP480 |
15.
Design Issue:
The IOP 480 Data Book indicates compliance with the PCI Power Management
Interface Specification revision 1.1, however the PMC register description is
compliant with revision 1.0. The IOP 480 can support either revision. The only
differences between these revisions, with respect to IOP 480 support, are the
Version bits [2:0] value (programmable by EEPROM or by local bus processor),
and the descriptions for bits [8:6, 4] for which the values are read-only and return
a value of 0 regardless of revision. The Version bits value (001b or 010b), which
has no effect on IOP 480 operation, is used by software to determine PMC
register format.
Recommendation:
PMC register descriptions for revisions 1.0 and 1.1 are listed below. If revision
1.1 rather than revision 1.0 is to be supported, program the PMC register (via
EEPROM or local bus processor) with the Version value (010b) to overwrite the
PMC register default value, by changing the 32-bit value at EEPROM offset E8h
or Local Bus offset 340h, from 00015401h to 00025401h.
Power Management Interface Specification version support
Register 10-27. (PMC; PCI:42h, LOC:342) Power Management Capabilities
(PCI Power Mgmt. r1.0)
Bit
Description
Read
Write
Value after
Reset
2:0
Version.
The value 001 indicates compliance with PCI Power
Mgmt. r1.0.
PCI Clock Required for PME# Signal.
Value of 1 indicates a
function relies on PCI clock presence for PME# operation. The
IOP480 does not require the PCI clock for PME#, so this bit
should set to 0.
Auxiliary Power Source.
Because the IOP 480 does not
support PME# while in a D3cold state, this bit is always set to 0.
Device-Specific Initialization (DSI).
Value of 1indicates the
IOP 480 requires special initialization following a transition to a
D0 uninitialized state before a generic class device driver is able
to use it.
Reserved.
D1_Support.
Value of 1 indicates the IOP 480 supports the D1
power state.
D2_Support.
Value of 1 indicates the IOP 480 supports the D2
power state.
PME Support.
Indicates power states in which the IOP 480
may assert PME#. Values:
XXXX1 = PME# can be asserted from D0
XXX1X = PME# can be asserted from D1
XX1XX = PME# can be asserted from D2
X1XXX = PME# can be asserted from D3hot
XXXXX = PME# cannot be asserted from D3cold
Yes
L, E
001
3
Yes
L, E
0
4
Yes
No
0
5
Yes
L, E
0
8:6
Yes
No
000
9
Yes
No
0
10
Yes
No
0
15:11
Yes
[14:11]:
L, E
[15]: No
00000
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
-
10-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IOS62C256-70U | IC-SM-256K CMOS SRAM |
| IP-ED8B10B | Telecomm/Datacomm |
| IP100 | PCI 10/100M Single Chip Ethernet Controller |
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IOPROJECTPRO | 制造商:Opto 22 功能描述:IOPROJECT PROFESSIONAL SOFTWARE SUITE, Kit Contents:Professional software suite, |
| IOPS-66-3610 | 制造商:IBase Technology (USA) Inc. 功能描述:OPS,CI5 3610ME,40G SSD,4GB RAM - Bulk |
| IOPS-76-3610 | 制造商:IBase Technology (USA) Inc. 功能描述:OPS,I5 3610ME,8G RAM,40G MSATA - Bulk |
| IOR000B20 | 制造商:Amphenol PCD 功能描述:DIN-RAIL INTERFACE MODULE PRODUCT -SEE CATALOG - Bulk |
| IOR000B30 | 制造商:Amphenol PCD 功能描述:DIN-RAIL INTERFACE MODULE PRODUCT -SEE CATALOG - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。