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參數(shù)資料
| 型號： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說明 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 245K |
| 代理商： | IOP480 |
The response of the IOP 480 PCI input buffers were simulated under various
extreme configurations. For example, with a 12” PCI trace length, 90 Ohms
bus impedance, 0 degrees Celsius, 3.6 Volts and being driven by a strong
output buffer (the IOP 480 output buffer has 35 Ohm output impedance), the
IOP 480 correctly interpreted the distorted digital waveform into the correct
ideal digital waveform. Graphs of this and other waveforms are available from
your PLX Area Sales Managers or FAEs.
Therefore, if the IOP 480 is part of a 3.3 Volt circuit that connects to other PCI
devices, it will properly interpret distorted signals. If there are non-IOP 480
devices on the PCI bus, they will also be able to interpret distorted signals
properly if they contain high clamp diodes.
7.
LCSx# Chip Select output delayed when IOP 480 is
initiating access to SRAM
Design Issue:
If DRAM refresh cycles are enabled (default), ongoing refresh cycles will preempt
LCSx# assertion. When the IOP 480 is about to initiate a cycle on the local bus
(in one of the LCSx# regions), DRAM refresh cycles may come in and jump
ahead of the LCSx# assertion. In this case, ADS#, ALE, and the local address
will still be generated, but LCSx# will not be generated until the refresh cycle is
completed. Any data being transferred will remain on the bus during this time
(waiting for READY#), so as a result there is no impact to the data transfer.
However, the multiplexed address on the LAD bus may have changed to data by
the time LCSx# is finally generated (when the refresh cycle has ended).
Recommendation:
1. Latch the de-multiplexed address on the MA bus instead of the LAD bus.
2. Always latch addresses with ADS# or ALE regardless of LCSx#.
3. Turn off refresh cycles when not using DRAM.
8.
CompactPCI Hot Swap Insertion Bit Status
Design Issue:
The IOP 480 Hot Swap insertion bit (HSCSR[7]) defaults to zero (0) after reset.
This can be considered a violation of PICMG 2.1 R1.0 CompactPCI Hot Swap
specification. This condition will cause a problem if the board switch is closed
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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