- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IOP480 I/O Processor|IOP 480 Design Notes PDF資料下載
參數(shù)資料
| 型號： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計說明 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 245K |
| 代理商： | IOP480 |
Recommendation:
Disable queue prefetching for the Messaging Unit by disabling the QSR register
bits (QSR[2]=0 and QSR[3]=0, the default values).
11.
Local Bus Timeout with SDRAM
Design Issue:
When a local bus transaction attempts to access an invalid address, the local bus
timeout feature in the IOP 480 can be used to avoid hanging the local bus.
However, when a local bus timeout occurs when there is SDRAM in the system,
this will cause the SDRAM state machine back to the POWER ON state,
requiring a re-initialization to start up again. When the SDRAM is in the POWER
ON state, a refresh request cannot be issued, so that when the IOP 480 refresh
timer expires, the refresh request will be logged but not completed. This will
preclude any other transaction onto the local bus, and the local bus will hang.
Recommendations:
1. If using the IOP 480 with SDRAM, do not count on the local bus timeout
feature to be able to recover from invalid address accesses.
2. Use software workarounds to recover from this condition.
12.
WAIT# input signal when using the Memory Controller
Design Issue:
The WAIT# input signal is not recognized by the IOP480 memory controller
during external local bus master transactions. Therefore, when WAIT# is
asserted by the external local bus master during such a transaction, the memory
controller will continue to carry out the transaction, ignoring the WAIT# input
signal.
Recommendation:
The following solution should be implemented with external glue logic:
a) Monitor the local bus address and WAIT#.
b) If WAIT# is asserted to the IOP 480 while the IOP 480 memory controller
is performing a transaction initiated by an external local bus master, assert
BLAST# (to the IOP480) and assert a BOFF# (to the external master).
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
-
7-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IOS62C256-70U | IC-SM-256K CMOS SRAM |
| IP-ED8B10B | Telecomm/Datacomm |
| IP100 | PCI 10/100M Single Chip Ethernet Controller |
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IOPROJECTPRO | 制造商:Opto 22 功能描述:IOPROJECT PROFESSIONAL SOFTWARE SUITE, Kit Contents:Professional software suite, |
| IOPS-66-3610 | 制造商:IBase Technology (USA) Inc. 功能描述:OPS,CI5 3610ME,40G SSD,4GB RAM - Bulk |
| IOPS-76-3610 | 制造商:IBase Technology (USA) Inc. 功能描述:OPS,I5 3610ME,8G RAM,40G MSATA - Bulk |
| IOR000B20 | 制造商:Amphenol PCD 功能描述:DIN-RAIL INTERFACE MODULE PRODUCT -SEE CATALOG - Bulk |
| IOR000B30 | 制造商:Amphenol PCD 功能描述:DIN-RAIL INTERFACE MODULE PRODUCT -SEE CATALOG - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。