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參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說(shuō)明 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | IOP480 |
Register 17-63. (PCICTL; PCI:98h, LOC:98h) PCI Bus Control
Bit
Description
Read
Write
Value
after
Reset
25
PCI r2.1
Features Enable.
When set to 1, the IOP 480
performs all PCI Read and Write transactions in compliance
with PCI r2.1. Setting this bit enables Delayed Reads, 2
15
PCI Clock timeout on Retries, 16- and 8-clock PCI latency
rules, and enables the option to select PCI Read No Write
Mode (Retries for writes) (bit [25]) and/or PCI Read with
Write Flush Mode (bit [26]). Refer to Section 4.5 for
additional information.
Value of 0 causes TRDY# to remain de-asserted on reads
until Read data is available. If Read data is not available
before the PCI Target Retry Delay Clocks counter
(LBRD0[31:28]) expires, a PCI Retry is issued.
P, L
P, L, E
1
4.5 PCI r2.1 Features Enable
The IOP 480 can be programmed through the PCI r2.1 Features Enable bit (PCICTL[25])
to perform all PCI Read/Write transactions in compliance to PCI r2.1 (and PCI r2.2). The
following IOP 480 behavior occurs when PCICTL[25] = 1.
4.5.1 Direct Slave Delayed Read Mode
PCI Bus single cycle aligned or unaligned 32-bit Direct Slave Read transactions always
result in a 1-Lword single cycle transfer on the Local Bus, with corresponding Local
Address and Byte Enables (LBE[3:0]#) asserted to reflect the PCI Byte Enables
(C/BE[3:0]#), unless the PCI Read Ahead Mode bit is enabled (PCICTL[22] = 1) (refer to
Section 4.6). This causes the IOP 480 to Retry all PCI Bus Read requests that follow,
until the original PCI Address and Byte Enables (C/BE[3:0]#) are matched.
4.5.2 2
15
PCI Clock Timeout
If a PCI Master does not complete its originally requested Direct Slave Delayed Read
transfer, the IOP 480 flushes the Direct Slave Read FIFO after 2
15
PCI clocks and will
grant an access to a new Direct Slave Read access. The IOP 480 Retries all other Direct
Slave Read accesses that occur before the 2
15
PCI clock timeout.
4.5.3 PCI r2.1 16- and 8- clock rule
The IOP 480 guarantees that if the first Direct Slave Write data cannot be accepted by
the IOP 480 and/or the first Direct Slave Read data cannot be returned by the IOP 480
within 16 PCI clocks from the beginning of the Direct Slave cycle (FRAME# asserted), the
IOP 480 issues a Retry (STOP# asserted) to the PCI Bus. During successful Direct
Slave Read and/or Direct Slave Write accesses, the subsequent data after the first
access is accepted for writes or returned for reads in 8 PCI clocks (TRDY# asserted).
Otherwise, the IOP 480 issues a PCI disconnect (STOP# asserted) to the PCI Master.
In addition, setting the PCI r2.1 Features Enable bit (PCICTL[25] = 1) allows optional
enabling of the following PCI r2.1 functions:
Retry PCI Writes During Pending Reads (PCICTL[24])
Flush Pending Reads on PCI Writes (PCICTL[23])
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
-
9-
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