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參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說(shuō)明 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 245K |
| 代理商： | IOP480 |
prior to reset (RST#) being negated, or if the system has been powered up with
the IOP 480 inserted.
Recommendation:
1. The board switch needs to be closed after PCI reset (RST#) is negated.
2. Software should always choose an Extraction procedure for the safe
termination of the CompactPCI Hot Swap adapter from the backplane.
9.
DMPAF# (Direct Master Programmable Almost Full)
negation timing
Specification Clarification:
The multiplexed pin LCS0#/DMPAF# is configured for DMPAF# output
functionality if the Local Bus Control register is set to 1 (LOCCTL[0]=1). The
default pin configuration is LCS0# functionality.
DMPAF# pin output assertion relies on the programmable value in DMPBAM
[12:8] to determine when to signal that the Direct Master Write FIFO is almost
full. After DMPAF# assertion, the IOP 480 negates the DMPAF# pin upon the last
word of the transfer entering into the Data Out Holding Register. The DMPAF#
signal indicates the Direct Master Write FIFO status, not the completion of the
transfer status.
10.
Messaging Unit data corruption if Queue Prefetch (Inbound
Free List FIFO Prefetch and/or Outbound Post List FIFO
Prefetch) is enabled
Design Issue:
When the Messaging Unit is enabled (MQCR[0]=1), the Inbound Free List FIFO
holds the message frame addresses (MFA) of available message Frames
(available to an external PCI agent) in shared Local memory. The Outbound Post
List FIFO holds the MFA of all currently posted messages (destined to an
external PCI agent) that are in shared Local memory.
To reduce read latency, queue prefetching can be enabled (QSR[2]=1 and/or
QSR[3]=1). However, if queue prefetching is enabled, the Messaging Unit data
can return incorrect data due to internal updating of the pointers.
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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