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參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說(shuō)明 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | IOP480 |
13
ALE Output Timing
14
PCI Delayed Read Mode bit (PCICTL[25])
15
Power Management Interface Specification version support
D.
Design Notes
1.
End-of-Transfer (EOT) During Chaining DMA End Link
Mode with Write-back
Design Issue:
When write back cycles are enabled (C0MODE[16]=1 and/or C1MODE[16]=1)
during DMA transfers with chaining enabled (C0MODE[9]=1 and/or
C1MODE[9]=1), the IOP 480 will write back to the DMA descriptor a value of zero
in the byte count field. However, if the EOTx# End Link mode is also enabled
(C0MODE[20]=1 and/or C1MODE[20]=1) and an EOTx# occurs right as the last
data in the DMA link has been transferred, the subsequent write back of zero
happens twice. Both write backs will write to the same address with the same
value 0 (zero).
Recommendation:
There should be no noticeable impact except for waveforms looking a bit odd.
2.
DMA Channel 2 with End-of-Transfer (EOTx#) asserted
coincident with ADS#
Design Issue:
If an End of Transfer (EOTx#) is asserted when the IOP 480 is asserting ADS#
during a DMA Channel 2 transfer, two (2) words will be transferred rather than
one (1) word before the DMA terminates. DMA 0 and 1, on the other hand,
transfer only one (1) word if an EOTx# is asserted on the same clock cycle as
ADS#.
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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