參數(shù)資料
型號(hào): IOP480
英文描述: I/O Processor|IOP 480 Design Notes
中文描述: I / O處理器|眼壓480設(shè)計(jì)說明
文件頁數(shù): 11/11頁
文件大?。?/td> 245K
代理商: IOP480
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
-
11-
Register 10-27. (PMC; PCI:42h, LOC:342) Power Management Capabilities
(PCI Power Mgmt. r1.1)
Bit
Description
Read
Write
Value after
Reset
2:0
Version.
The default value 001 indicates compliance with PCI
Power Mgmt. r1.1. To instead indicate PMC register format
compliance with Revision 1.1, this value should be set to 010.
PCI Clock Required for PME# Signal.
Value of 1 indicates a
function relies on PCI clock presence for PME# operation. The
IOP 480 does not require the PCI clock for PME#, so this bit
should set to 0.
Reserved.
Device-Specific Initialization (DSI).
Value of 1 indicates the
IOP 480 requires special initialization following a transition to a
D0 un-initialized state before a generic class device driver is
able to use it.
Aux_Current.
Supported by way of the PMDATA register per
PCI Power Mgmt. r1.1.
D1_Support.
Value of 1 indicates the IOP 480 supports the D1
power state.
D2_Support.
Value of 1 indicates the IOP 480 supports the D1
power state.
PME Support.
Indicates power states in which the IOP 480
may assert PME#. Values:
XXXX1 = PME# can be asserted from D0
XXX1X = PME# can be asserted from D1
XX1XX = PME# can be asserted from D2
X1XXX = PME# can be asserted from D3hot
XXXXX = PME# cannot be asserted from D3cold
Yes
Local
001
3
Yes
Local
0
4
Yes
No
0
5
Yes
L, E
0
8:6
Yes
No
000
9
Yes
L, E
0
10
Yes
L, E
0
15:11
Yes
[14:11]:
L, E
[15]: No
00000
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registered in some jurisdictions. All other product names that appear in this material are for identification purposes only
and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by
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specification.
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