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參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說明 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 245K |
| 代理商： | IOP480 |
3.
Design Issue:
The memory controller configuration registers allow settings for zero wait state
SRAM writes. However, the IOP 480 does not support zero wait state writes to
asynchronous SRAM on the local bus. Zero wait state reads from external
asynchronous SRAM are unaffected as they do not require the toggling of the
MWE# signal.
Recommendations:
1. Use 1 wait state writes when accessing external asynchronous SRAM
(WDD=1).
2. Use SDRAM instead of SRAM for fast accesses to memory.
3. Use SBSRAM.
4.
External local master write to IOP 480 internal
configuration registers with WAIT# being used to insert
wait states
Design Issue:
The WAIT# input can be used by an external local bus master to insert wait
states when accessing the IOP 480 internal configuration registers or when
accessing the PCI bus during Direct Master accesses.
During a configuration write, WAIT# must be asserted (by the external local
master) a minimum of two (2) clocks before READY# is asserted by the IOP 480,
for the IOP 480 to sense the WAIT# input. The earliest READY# will be asserted
is seven (7) clocks after the assertion of ADS#. Therefore, in order to ensure that
WAIT# is recognized by the IOP 480, WAIT# should be asserted no later than
five (5) clocks after the assertion of ADS#. Any assertion of WAIT# more than
five (5) clocks after the assertion of ADS# may be ignored by the IOP 480.
If the IOP 480 does not sense WAIT# it will simply assert READY# for one clock
(and think the cycle has ended) instead of waiting until WAIT# has been negated.
This problem applies only when an external local master is writing to the IOP 480
internal configuration registers.
Zero Wait State SRAM Writes
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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