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參數(shù)資料
| 型號(hào)： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設(shè)計(jì)說明 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 245K |
| 代理商： | IOP480 |
13.
Data Book Change:
Figure 19-1 in the IOP 480 Data Book r1.0 and r2.0 shows a Timing Diagram for
the ALE signal that is incorrect. ALE timing is dependent on the Local Clock
period, which was not shown in the existing diagram.
1. The following diagram correctly shows the ALE timing specifications:
ALE Output Timing
1.5V
1.5V
Address Bus
4.3 / 9.3
3.7 / 8.3
4.0 / 10.0
Local Clock
ALE
LC
high
+ 0.6/1.0
LC
high
3.8 / 8.6
14.
Data Book Change:
The name for the PCI Bus Control register bit 25 (PCICTL[25]) is changed from
“PCI Delayed Read Mode” to “PCI r2.1 Features Enable”. IOP 480 Data Book
section 4.5, and the PCICTL[25] register bit description, are revised:
PCI Delayed Read Mode bit (PCICTL[25])
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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8-
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