參數(shù)資料
型號: IP101
英文描述: PHY 10/100M Single Chip Fast Ethernet Transceiver
中文描述: 單芯片物理層10/100M自適應(yīng)快速以太網(wǎng)收發(fā)器
文件頁數(shù): 16/33頁
文件大小: 821K
代理商: IP101
IP101
6.0 Register Descriptions
(continued)
Register 17 : PHY Interrupt Ctrl/Status Register
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
16 / 33
IP101-DS-R0.02
Feb. 24, 2003
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Address
Name
Description/Usage
Default value (h):
0E00
15
INTR pin
used
Set high to enable pin48 as an interrupt pin, or high
impedance is presented at this pin
0, R/W
14:12
Reserved
11
All Mask
When this bit is set high, changes in all events will not cause
an interrupt
1, R/W
10
Speed Mask
When this bit is set high, changes in speed mode will not
cause an interrupt
1, R/W
9
Duplex Mask
When this bit is set high, changes in duplex mode will not
cause an interrupt
1, R/W
8
Link Mask
When this bit is set high, changes in link status will not cause
an interrupt
1, R/W
7
Arbiter State
Enable
When this bit is set high, changes in N-WAY arbiter state
machine will cause an interrupt
0, R/W
6
Arbiter State
Change
Flag to indicate N-WAY arbiter change interrupt
0, R/W
5:3
Reserved
0, R/W
2
Link Status
Change
Flag to indicate link status change interrupt
0, R/W
1
Speed
Change
Flag to indicate speed change interrupt
0, R/W
0
Duplex
Change
Flag to indicate duplex change interrupt
0, R/W
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