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參數(shù)資料
| 型號： | IP101 |
| 英文描述： | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| 中文描述： | 單芯片物理層10/100M自適應(yīng)快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 23/33頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IP101 |
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IP101
9.0 Layout Guideline
General Layout Guideline
Best performance depends on good layout. The
following recommendation steps will help customer to
gain maximum performance.
Create good power source to minimize noise from
switching power source.
-
All components are qualified, especially high noise
component, such as clock component.
-
Use bulk capacitors between power plane and
ground plane for 4 layers board, signals trace on
component and bottom side, power plane on third
layer, and ground layer on second layer.
-
Use decoupling capacitors to decouple high
frequency noise between chip’ s power and ground,
must be as close as possible to IP101.
-
The clock trace length to IP101 must be equal the
clock trace length to MAC.
-
Use guard traces to protect clock traces if possible
-
Avoid signals path parallel to clock signals path,
because clock signals will interference with other
parallel signals, degrading signal quality, such as
MDC and X1signals.
-
The clock must be low jitter with less than 0.5ns for
25/50/125Mhz 100ppm.
-
Avoid highly speed signal across ground gap to
IP101-DS-R0.02
Feb. 24, 2003
23 / 33
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
prevent large EMI effect.
-
Keep ground region as one continuous and
unbroken plane.
-
Place a gap between the system and chassis
grounds.
-
No any ground loop exists on the chassis ground.
Twisted Pair recommendation
When routing the TD+/- signal traces from IP101 to
transformer, the traces should be as short as possible,
the termination resistors should be as close as possible
to the output of the TD+/- pair of IP101. Center tap of
primary winding of these transformers must be
connected
to
analog
2.5V
recommended that RD+/- trace pair be route such that
the space between it and others is three times space,
which can separate individual traces from one another.
It is recommended that offers chassis ground in the
area between transformer and media connector (RJ-45
port), this isolates the analog signals from external
noise sources and reduces EMI effect. Note the usage
of the vias, it is best not use via to place anywhere
other than in close proximity to device, in order to
minimize impedance variations in a given signal trace.
respectively.
It
is
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IP101ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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