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參數(shù)資料
| 型號： | IP101 |
| 英文描述： | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| 中文描述： | 單芯片物理層10/100M自適應快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IP101 |
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IP101
6.0 Register Descriptions
This section will explain the meaning and usage for each of the registers available in the IP101.
The first 7 registers, i.e., Register 0 to Register 6, are defined according to IEEE 802.3 standard, while the rest
registers are defined by IC Plus Corp. and they are for internal use or reserved for other usage.
The first 2 registers contain the basic control and status register defined by IEEE standard.
Each register has its own default value, and it is placed in the right block of each register title.
Register 0 : MII Control Register
IP101-DS-R0.02
Feb. 24, 2003
9 / 33
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Address
Name
Description/Usage
Default value (h):
3100
15
Reset
When set, this action will bring both status and control registers
of the PHY to default state. This bit is self-clearing.
1 = Software reset
0 = Normal operation
0, RW
14
Loop-back
This bit enables loop-back of transmit data to the receive data
path, i.e., TXD to RXD.
1 = enable loop-back
0 = normal operation
0, RW
13
Speed
Selection
This bit sets the speed of transmission.
1 = 100Mbps
0 = 10Mbps
During 100Base-FX mode, and when this bit = 1, it indicates
read only.
1, RW
12
Auto-
Negotiation
Enable
This bit determines the auto-negotiation function.
1 = enable auto-negotiation; bits 13 and 8 will be ignored.
0 = disable auto-negotiation; bits 13 and 0:<8> will determine
the link speed and the data transfer mode, under this condition.
When 100Base-FX mode is enabled, and this bit=0, it indicates
read only.
1, RW
11
Power Down
This bit will turn down the power of the PHY chip and the
internal crystal oscillator circuit if this bit is enabled. The MDC
and MDIO are still activated for accessing to the MAC.
1 = power down
0 = normal operation
0, RW
10
Isolate
1=electrically Isolate PHY from MII but not isolate MDC and MDIO
0=normal operation
0,RW
9
Restart Auto-
Negotiation
This bit allows the Nway auto-negotiation function to be reset.
1 = restart auto-negotiation
0 = normal operation
0, RW
8
Duplex Mode
This bit sets the duplex mode if auto-negotiation is disabled (bit
12=0)
1 = full duplex
0 = half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.(1: Full duplex, 0: Half duplex)
When 100Base-FX mode is enabled, this bit can be set
through the MDC/MDIO SMI interface or DUPLEX pin.
1, RW
7
Collision Test
1=enable COL signal test
0=disable COL signal test
0,RW
6:0
Reserved
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP101ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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