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參數(shù)資料
| 型號： | IP101 |
| 英文描述： | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| 中文描述： | 單芯片物理層10/100M自適應(yīng)快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IP101 |
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IP101
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
18 / 33
IP101-DS-R0.02
Feb. 24, 2003
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Transmission Description
10Mbps Transmit flow path:
TXD
g
Parallel to Serial
g
NRZI/Manchester Encoder
g
D/A & line driver
g
TXO
After MAC passes data to PHY via 4 bits nibbles, the
data are serialized in the parallel to serial converter.
The converter outputs NRZI coded data which the data
are then mapped to Manchester code within the
Manchester Encoder. Before transmitting to the
physical medium, the Manchester coded data are
shaped by D/A converter to fit the physical medium.
10Mbps Receive:
RXI
g
Squelch
g
Clock Recovery
g
Manchester/NRZ
Decoder
g
Serial to Parallel
g
RXD
The squelch block determines valid data from both AC
timing and DC amplitude measurement. When a valid
data is present in the medium, squelch block will
generate a signal to indicate the data has received. The
data receive are coded in Manchester form, and are
decoded in the Manchester to NRZ Decoder. Then the
data are mapped to 4 bits nibbles and transmitted onto
MAC interface.
100Mbps TX Transmit:
TXD
g
4B/5B Encoder
g
Scrambler
g
NRZI/MLT-3
Encoder
g
D/A & line driver
g
TXO
The major differences between 10Mbps transmission
and
100Mbps
transmission
transmission requires to be coded from 4-bit wide
nibbles to 5 bits wide data coding, and after that the
data are scrambled through scrambler to reduce the
radiated energy generated by the 4B/5B conversion.
Then the data is converted into NRZI form and again
from NRZI coded form into MLT-3 form. The MLT-3
data form is fed into D/A converter and shaped to fit the
physical medium transmission.
100Mbps TX Receive:
RXI
g
DSP
g
Serial to Parallel
g
Descrambler
g
4B/5B Decoder
g
RXD
The received data first go through DSP engines which
includes adaptive equalizer and base-line wander
correction mechanism. The adaptive equalizer will
compensate the loss of signals during the transmission,
while base-line wander monitors and corrects the
equalization process. If a valid data is detected then the
data are parallelized in Serial to Parallel block, which it
converts NRZI coded data form back to scrambled data.
are
that
100Mbps
The scrambled data are descrambled and converted
back to 4 bits–wide format data and then feed into
MAC.
100Mbps FX Transmit:
TXD
g
4B/5B Encoder
g
Parallel to Serial
g
D/A &
line driver
g
TXO
Fiber transmission first encodes the data into 5bits
wide data format. The data are then serialized and then
converted to fit the physical medium transmission.
100Mbps FX Receive:
RXI
g
DSP (Clock Recovery)
g
Serial to Parallel
g
4B/5B Decoder
g
RXD
The received data contains the information periodically,
and for Fiber Receive, the Clock recovery extracts the
data from the clock cycle. The extracted data is
parallelized into 5-bits wide data, which are then
converted back to nibble-formed information.
MII and Management Control Interface
Media Independent Interface (MII) is described in
clause 22 in the IEEE 802.3u standard. The main
function of this interface is to provide a communication
path between PHY and MAC/Repeater. It can operate
either in 10Mb or 100Mb environment, and operate at
2.5MHz frequency for 10Mb clock data rate or 25MHz
frequency for 100Mb data rate transmission. MII
consists of 4 bit wide data path for both transmit and
receive. The transmission pins consists of TXD[3:0],
TX_EN and TXC, and at receiving MII pins have
RXD[3:0], RXER, RX_DV and RXC. The Management
control
pins
include
MDC
Management Data Clock, provides management data
clock at maximum of 10MHz as a reference for MDIO,
Management Data Input/Output. CRS, Carrier Sense,
is used for signaling data transmission is in process
while COL, Collision, is used for signaling the
occurrence of collision during transmission.
Transmitting a packet, MAC will first assert TX_EN and
convert the information into 4 bit wide data and then
pass the data to IP101. IP101 will sample the data
according to TX_CLK until TX_EN is low.
While receiving a packet, IP101 asserts RX_DV high
when data present in the medium through RXD[3:0] bus
lines. IP101 samples received data according to
RX_CLK until the medium is back to idle state.
and
MDIO.
MDC,
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相關(guān)代理商/技術(shù)參數(shù) |
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| IP101ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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| IP101ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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