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參數(shù)資料
| 型號： | IP101 |
| 英文描述： | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| 中文描述： | 單芯片物理層10/100M自適應快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IP101 |
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IP101
5.0 Pin Descriptions
Type
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
4 / 33
IP101-DS-R0.02
Feb. 24, 2003
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Description
LI
Latched Input in power up or reset
I/O
Bi-directional input and output
I
Input
O
Output
Type
Description
PD
Internal Pull-Down
PU
Internal Pull-Up
P
Power
OD
Open Drain
Pin no.
Label
Type
Description
MII and PCS Interface - Management Interface Pins
25
MDC
I
Management Data Interface Clock:
This pin provides a clock
reference to MDIO. The clock rate can be up to 10MHz.
26
MDIO
I/O
Management Data interface Input/Output:
The function of this
pin is to transfer management information between PHY and
MAC.
MII and PCS Interface – Media Independent Interface (MII) Pins
2
TX_EN
I
(PD)
Transmit Enable:
This pin is an active high input. At high status,
it indicates the nibble data in TXD[3:0] is valid.
7
TX_CLK
O
Transmit Clock:
This pin provides a continuous 25MHz clock at
100Mbps and 2.5Mbps as timing reference for TXD[3:0] and
TX_EN when the chip operates under MII and SNI modes. This
pin is an input pin operates as RMII reference clock (REF_CLK)
under RMII mode.
3, 4, 5, 6
TXD[3:0]
I
Transmit Data:
When TX_EN is set low, MAC will transmit data
through these 4 lines to PHY which the transmission is
synchronizing with TX_CLK.
22
RX_DV
O
Receive Data Valid:
At high status stands for data flow is present
within RXD[0:3] lines and low means no data exchange occurred.
16
RX_CLK
O
Receive Clock:
This pin provides 25MHz for 100Mbps
transmission or 2.5Mhz for 10Mbps transmission and RX_DV pin
uses this pin as its reference under MII or SNI mode. While under
RMII mode this pin is driven low.
18, 19,
20, 21
RXD[3:0]
O
Receive Data:
These 4 data lines are transmission path for PHY
to send data to MAC and they are synchronizing with RX_CLK.
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相關代理商/技術參數(shù) |
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| IP101ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
| IP101ALF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single port 10/100 Fast Ethernet Transceiver |
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