參數(shù)資料
型號: IP101
英文描述: PHY 10/100M Single Chip Fast Ethernet Transceiver
中文描述: 單芯片物理層10/100M自適應(yīng)快速以太網(wǎng)收發(fā)器
文件頁數(shù): 25/33頁
文件大?。?/td> 821K
代理商: IP101
IP101
10.1 MII interface with UTP
(continued)
IP101-DS-R0.02
Feb. 24, 2003
25 / 33
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
C22
10U
Power: 5V ~ 3.3V
P0PHYAD3/LED3
R20
510 ohm
* : Optional ,but recommended
Hardwire Configuration network:
C19
*
C21
REGOUT
D3
LED
R28
5.1K
L2
BEAD
R29
510 ohm
VDD33
P0PHYAD4/LED4
REGOUT and REGIN connection
LED and PHY address Configuration
C18
D2
LED
C24
10U
VDD33
R21
5.1K
AVDD33
R27
510 ohm
LED0 LED1 LED2 LED3 LED4
Analog and
Digital 3.3V
connection
D1
LED
R19
5.1K
REGIN
D5
LED
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be
connected to VDD or GND directly.
P0PHYAD1/LED1
R22
510 ohm
P0PHYAD2/LED2
C16
This schematic sets PHY address to
00001b.
*
L1
BEAD SMD
P0PHYAD0/LED0
R23
5.1K
MII UTP
<RevCode>
IP101 Chip Circuit Diagram
Document Number
A
3
3
Tuesday, February 18, 2003
Title
Size
Rev
Date:
Sheet
of
VDD33
C20
0.1U
REGOUT
R24
510 ohm
U4
LM1117
3
2
1
INPUT
OUTPUT
ADJ/GND
D4
LED
VCC5V
R26
5.1K
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