
IP101
5.0 Pin Descriptions
(continued)
Pin no.
Copyright
2003, IC Plus Corp.
Confidential, All rights reserved.
Advanced, Specification subject to change without notice.
8 / 33
IP101-DS-R0.02
Feb. 24, 2003
NOT APPROVED BY TECHNICAL DOCUMENT CONTROL
Label
Type
Description
Clock and Miscellaneous - Miscellaneous Pins
I
RESET_N:
Enable a low status signal will reset the chip. For a
complete reset function, this pin must be asserted low for at least
10ms.
42
RESET_N
48
INTR
I/O
(OD)
Interrupt Pin:
When the MII register 17:<15> is set to high, this
pin is used as an interrupt pin (Notice: this is an open drain output,
so an external pulled-up resistor is needed)
27
TEST_ON
(PD)
Test Enable:
Set this pin to high to enable test mode, while for
normal operation, this pin does not need to be connected. (An
internal weak pulled-down is used to disable test mode as a
default)
28
ISET
I
Transmit Bias Resistor Connection:
This pin should be
connected to GND via a
6.2KO (1%) resistor to define driving
current for transmit DAC. The resistance value may be changed,
depending on experimental results of the IP101.
Power and Ground
32
REGOUT
P
Regulator Power Output:
This is a regulator power output for
IP101 digital circuitry.
36
AVDD33
P
3.3V Analog power input:
This is a 3.3V power supply for analog
circuitry, and it should be decoupled carefully.
29,35
AGND
P
Analog Ground:
These 2 pins should connect to motherboard’s
GND.
8
REGIN
P
Regulator Power Input:
This is a regulator power input from
Pin32. No external regulator needed.
14
DVDD33
P
3.3V Digital Power input:
This is a 3.3V power supply for digital
circuitry.
11,17,45
DGND
P
Digital Ground:
These 3 pins should connect to motherboard’s
GND.