參數(shù)資料
型號： ISP1362
廠商： NXP Semiconductors N.V.
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù)： 110/150頁
文件大?。?/td> 647K
代理商： ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
110 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
the Hc
μ
PInterrupt register) to indicate a time-out situation, provided
HcATLPTDDoneMap is currently 0x0000 0000.
Table 105
shows the bit allocation of
the HcATLPTDDone register.
Remark:
If the time-out indication is not required by software, or there is no active
PTD in the ATL buffer, write 0x0000 to this register.
Code (Hex): 52
—
read
Code (Hex): D2
—
write
16. Device Controller (DC) registers
The functions and registers of the DC are accessed using commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
Table 107
.
A complete access consists of two phases:
1.
Command phase
: when address pin A0 = HIGH, the DC interprets the data on
the lower byte of the bus (bits D7 to D0) as a command code. Commands without
a data phase are immediately executed.
2.
Data phase (optional)
: when address pin A0 = LOW, the DC transfers the data
on the bus to or from a register or endpoint buffer memory. In case of multi-byte
registers, the least signi
fi
cant byte or word are accessed
fi
rst.
The following applies to a register or buffer memory access in the 16-bit bus mode:
The upper byte (bits D15 to D8) in the command phase or the unde
fi
ned byte in
the data phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
Table 105: HcATLPTDDoneThresholdTimeOut register: bit allocation
Bit
15
14
Symbol
Reset
-
-
Access
-
-
Bit
7
6
Symbol
Reset
0
0
Access
R/W
R/W
13
12
11
10
9
8
reserved
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
PTDDoneTimeOut[7:0]
0
R/W
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
Table 106: HcATLPTDDoneThresholdTimeOut register: bit description
Bit
Symbol
15 to 8
-
7 to 0
PTDDoneTimeOut[7:0]
Description
reserved
Maximum allowable time in ms for the HC to retry a
transaction with NAK returned.
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