參數(shù)資料
型號(hào)： ISP1362
廠商： NXP Semiconductors N.V.
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù)： 76/150頁
文件大小： 647K
代理商： ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
76 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.1.6
HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
Table 43:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
31
30
MIE
0
R/W
23
22
29
28
27
26
25
24
reserved
-
-
19
-
-
-
-
-
-
-
-
-
-
-
-
21
20
18
17
16
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
-
8
15
14
13
12
11
10
reserved
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
reserved
-
-
RHSC
0
R/W
FNO
0
R/W
UE
0
R/W
RD
0
R/W
SF
0
R/W
reserved
-
-
SO
0
R/W
Table 44:
Bit
31
HcInterruptEnable register: bit description
Symbol
Description
MIE
MasterInterruptEnable
by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events speci
fi
ed in other
bits of this register.
-
reserved
RHSC
0
—
ignore
30 to 7
6
1
—
enable interrupt generation because of Root Hub Status
Change
0
—
ignore
5
FNO
1
—
enable interrupt generation because of Frame Number
Over
fl
ow
0
—
ignore
4
UE
1
—
enable interrupt generation because of Unrecoverable Error
0
—
ignore
3
RD
1
—
enable interrupt generation because of Resume Detect
0
—
ignore
2
SF
1
—
enable interrupt generation because of Start of Frame
reserved
0
—
ignore
1
0
-
SO
1
—
enable interrupt generation because of Scheduling Overrun
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