參數(shù)資料
型號： ISP1362
廠商： NXP Semiconductors N.V.
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù)： 27/150頁
文件大?。?/td> 647K
代理商： ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
27 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Hc
μ
PInterrupt
–
Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set
when the DMA transfer is complete.
HcTransferCounter
–
If DMACounterEnable of the HcDMACon
fi
guration register is set (that is, the
DMA counter is enabled), HcTransferCounter must be set to the number of
bytes to be transferred.
HcDMACon
fi
guration
–
Read or write DMA (bit 0)
–
Targeted buffer
:
ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
–
DMA enable or disable (bit 4)
–
Burst length (bits 5 to 6)
–
DMA counter enable (bit 7).
Remark:
Con
fi
gure the HcDMACon
fi
guration register only after you have con
fi
gured
all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in
this register is set.
9.6.2
Combining the two DMA channels
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to
the OneDMA bit of the HcHardwareCon
fi
guration register. If this option is enabled,
the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and
DREQ active HIGH.
9.7 Interrupts
Various events in the HC, the DC and the OTG controller can be programmed to
generate a hardware interrupt. By default, the interrupt generated by the HC and the
OTG controller is routed out at the INT1 pin and the interrupt generated by the DC is
routed out at the INT2 pin.
9.7.1
Interrupt in the HC and the OTG controller
There are two levels of interrupts represented by level 1 and level 2 (see
Figure 14
).
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相關代理商/技術參數(shù)
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