參數(shù)資料
型號: ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 78/150頁
文件大?。?/td> 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
78 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.2 HC Frame Counter registers
15.2.1
HcFmInterval register (R/W: 0DH/8DH)
The HcFmInterval register (bit allocation:
Table 47
) contains a 14-bit value that
indicates the bit time interval in a frame between two consecutive SOFs. In addition, it
contains a 15-bit value indicating the full-speed maximum packet size that the HC
may transmit or receive without causing a scheduling overrun. The HCD may carry
out minor adjustments on FrameInterval by writing a new value over the present one
at each SOF. This provides the programmability necessary for the HC to synchronize
with an external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D
read
Code (Hex): 8D
write
2
SF
0
ignore
1
disable interrupt generation because of Start of Frame
reserved
0
ignore
1
0
-
SO
1
disable interrupt generation because of Scheduling Overrun
Table 46:
Bit
HcInterruptDisable register: bit description
continued
Symbol
Description
Table 47:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
31
FIT
0
R/W
23
30
29
28
27
26
25
24
FSMPS[14:8]
0
R/W
19
FSMPS[7:0]
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
18
R/W
17
R/W
16
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
FI[13:8]
-
-
7
-
-
6
1
0
1
1
1
0
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
FI[7:0]
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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