參數(shù)資料
型號(hào): ISP1362
廠商: NXP Semiconductors N.V.
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: 單芯片通用串行總線和On - The - Go控制器
文件頁數(shù): 92/150頁
文件大?。?/td> 647K
代理商: ISP1362
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
92 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.4 HC DMA and interrupt control registers
15.4.1
HcHardwareCon
fi
guration register (R/W: 20H/A0H)
The bit allocation of the HcHardwareCon
fi
guration register is given in
Table 63
.
Code (Hex): 20
read
Code (Hex): A0
write
Table 63:
Bit
Symbol
HcHardwareCon
fi
guration register: bit allocation
15
14
Disable
Suspend_
Wakeup
Down
0
0
R/W
R/W
7
6
OneDMA
DACKInput
Polarity
13
12
11
10
9
8
Global
Power
Connect
PullDown
_DS2
0
R/W
5
DREQ
Output
Polarity
1
R/W
Connect
PullDown
_DS1
0
R/W
4
DataBusWidth[1:0]
Suspend
ClkNotStop
AnalogOC
Enable
OneINT
DACKMode
Reset
Access
Bit
Symbol
0
0
0
0
R/W
3
R/W
2
Interrupt
Output
Polarity
0
R/W
R/W
1
Interrupt
PinTrigger
R/W
0
InterruptPin
Enable
Reset
Access
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 64:
Bit
15
HcHardwareCon
fi
guration register: bit description
Symbol
Description
DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the
D_SUSPEND/D_WAKEUP and
H_SUSPEND/H_WAKEUP pins. Therefore, these pins
will always remain HIGH and pulling them LOW does
not wake up the HC and the DC.
GlobalPowerDown
Set this bit to logic 1 to reduce power consumption of
the OTG ATX in the suspend mode.
ConnectPullDown_DS2
0
disconnect built-in pull-down resistors on H_DM2
and H_DP2
14
13
1
connect built-in pull-down resistors on H_DM2
and H_DP2 for the downstream port 2
Remark:
Port 2 is always used as a host port.
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