參數(shù)資料
型號(hào): ISP1583ET1,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁數(shù): 19/100頁
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
24 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
8.16.1 Power-sharing mode
As can be seen in Figure 13, in power-sharing mode, VCC(3V3) is supplied by the output of
the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. VCC(I/O) is
supplied through the power source of the system. When the USB cable is plugged in, the
ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled.
The processor will experience continuous interrupt because the default status of the
interrupt pin when operating in sharing mode with VBUS not present is LOW. To overcome
this, implement external VBUS sensing circuitry. The output from the voltage regulator can
be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583.
Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N
pin. The minimum width of the reset pulse width must be 2 ms.
VCC(I/O) is system powered.
Fig 13. Power-sharing mode
Fig 14. Interrupt pin status during power off in power-sharing mode
004aaa458
ISP1583
5 V-to-3.3 V
USB
VOLTAGE
REGULATOR
to GPIO of processor
for sensing VBUS
1 M
VCC(3V3)
VCC(I/O)
VBUS
RPU
VBUS
1 F
1.5 k
004aaa459
VCC(I/O)
VCC(3V3)
INT
power off
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