參數(shù)資料
型號(hào)： ISP1583ET1,118
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁(yè)數(shù)： 38/100頁(yè)
文件大?。?/td> 508K
代理商： ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
41 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
buffer is automatically validated. The data packet will then be sent on the next IN token.
When it is necessary to validate the endpoint whose byte count is less than
MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the
Buffer Length register.
Remark: The buffer can automatically be validated by using the Buffer Length register
Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto
decremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in
the RX FIFO. When all bytes are read, buffer contents are automatically cleared. A new
data packet can then be received on the next OUT token. Buffer contents can also be
cleared using the Control Function register (bit CLBUF), when it is necessary to forcefully
clear contents.
Remark: The delay time from the Write Endpoint Index register to the Read Data Port
register must be at least 190 ns.
Remark: The delay time from the Write Endpoint Index register to the Write Data Port
register must be at least 100 ns.
9.3.4 Buffer Length register (address: 1Ch)
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit allocation is given in Table 41.
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see Table 45). A smaller value can be written when
required. After a bus reset, the Buffer Length register is made zero.
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer
Length register is not signicant. This register is useful only when transferring data that is
not a multiple of MaxPacketSize. The following two examples demonstrate the
signicance of the Buffer Length register.
Table 39.
Data Port register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATAPORT[15:8]
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATAPORT[7:0]
Reset
00000000
Bus reset
00000000
Access
R/W
Table 40.
Data Port register: bit description
Bit
Symbol
Description
15 to 8
DATAPORT[15:8] data (upper byte)
7 to 0
DATAPORT[7:0]
data (lower byte)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1583ET1-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET1TM 制造商:STMicroelectronics 功能描述:
ISP1583ET2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
ISP1583ET2,518 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET2-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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