參數(shù)資料
型號(hào)： ISP1583ET1,118
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁(yè)數(shù)： 36/100頁(yè)
文件大小： 508K
代理商： ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
39 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.3.2 Control Function register (address: 28h)
The Control Function register performs the buffer management on endpoints. It consists
of 1 byte, and the bit conguration is given in Table 37. Register bits can stall, clear or
validate any enabled endpoint. Before accessing this register, the Endpoint Index register
must rst be written to specify the target endpoint.
Table 35.
Endpoint Index register: bit description
Bit
Symbol
Description
7 to 6
-
reserved
5
EP0SETUP
Endpoint 0 Setup: Selects the SETUP buffer for endpoint 0.
0 — Data buffer
1 — SETUP buffer
Must be logic 0 for access to endpoints other than set-up token buffer.
4 to 1
ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of
buffer length, buffer status, control function, data port, endpoint type
and MaxPacketSize.
0
DIR
Direction: Sets the target endpoint as IN or OUT.
0 — Target endpoint refers to OUT (RX) FIFO
1 — Target endpoint refers to IN (TX) FIFO
Table 36.
Addressing of endpoint buffers
Buffer name
EP0SETUP
ENDPIDX
DIR
SETUP
1
00h
0
Control OUT
0
00h
0
Control IN
0
00h
1
Data OUT
0
0Xh
0
Data IN
0
0Xh
1
Table 37.
Control Function register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
CLBUF
VENDP
DSEN
STATUS
STALL
Reset
-
00000
Bus reset
-
00000
Access
-
R/W
W
R/W
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ISP1583ET1TM 制造商:STMicroelectronics 功能描述:
ISP1583ET2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
ISP1583ET2,518 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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