參數(shù)資料
型號(hào)： ISP1583ET1,118
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁數(shù)： 32/100頁
文件大?。?/td> 508K
代理商： ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
36 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.2.4.1
Session Request Protocol (SRP)
The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing,
followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS
pulsing.
The ISP1583 can initiate the B-device SRP by performing the following steps:
1. Set the OTG bit to start SRP.
2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG
register.
3. Start data-line pulsing: set bit DP of the OTG register to logic 1.
4. Wait for 5 ms to 10 ms.
5. Stop data-line pulsing: set bit DP of the OTG register to logic 0.
6. Start VBUS pulsing: set bit VP of the OTG register to logic 1.
7. Wait for 10 ms to 20 ms.
8. Stop VBUS pulsing: set bit VP of the OTG register to logic 0.
9. Discharge VBUS for about 30 ms: optional by using bit DISCV of the OTG register.
10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG
cleared.
11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus
enumeration.
The B-device must complete both data-line pulsing and VBUS pulsing within 100 ms.
Remark: When disabling OTG, data-line pulsing bit DP and VBUS pulsing bit VP must be
cleared by writing logic 0.
9.2.5 Interrupt Enable register (address: 14h)
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here
n represents the endpoint number. All interrupts can be globally disabled using bit
GLINTENA in the Mode register (see Table 24).
An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the
USB bus. The interrupt generation depends on Debug mode settings of bit elds
CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt
Conguration register.
All data IN transactions use the Transmit buffers (TX), which are handled by bits
DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which
are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT
and SETUP) are handled by bits CDBGMOD[1:0].
Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up
and high-speed status) can also be individually controlled. A bus reset disables all
enabled interrupts, except bit IEBRST (bus reset), which remains logic 1.
The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 32.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1583ET1-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET1TM 制造商:STMicroelectronics 功能描述:
ISP1583ET2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
ISP1583ET2,518 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET2-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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