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| 型號： | ISP1583ET1,118 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64 |
| 文件頁數(shù)： | 62/100頁 |
| 文件大小： | 508K |
| 代理商： | ISP1583ET1,118 |
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ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
63 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.5.5 Unlock Device register (address: 7Ch)
To protect registers from getting corrupted when the ISP1583 goes into suspend, the write
operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when
the chip resumes, the Unlock Device command must rst be issued to this register before
attempting to write to the rest of the registers. This is done by writing unlock code (AA37h)
to this register. The bit allocation of the Unlock Device register is given in Table 90.
When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you
do not need to issue the Unlock command because the microprocessor is powered and
therefore, the RW_N/RD_N, DS_N/WR_N and CS_N signals maintain their states.
When bit PWRON is logic 0, the RW_N/RD_N, DS_N/WR_N and CS_N signals are
oating because the microprocessor is not powered. To protect the ISP1583 registers
from being corrupted during suspend, register write is locked when the chip goes into
suspend. Therefore, you need to issue the Unlock command to unlock the ISP1583
registers.
9.5.6 Test Mode register (address: 84h)
This 1-byte register allows the rmware to set the DP and DM pins to predetermined
states for testing purposes. The bit allocation is given in Table 92.
Remark: Only one bit can be set at a time. Either bit FORCEHS or FORCEFS must be set
to logic 1 at a time. Of the four bits PRBS, KSTATE, JSTATE and SE0_NAK only one bit
must be set at a time. This must be implemented for the Hi-Speed USB logo compliance
testing. To exit test mode, power cycle is required.
Table 89.
Scratch register: bit description
Bit
Symbol
Description
15 to 8
SFIRH[7:0]
Scratch rmware information register (higher byte)
7 to 0
SFIRL[7:0]
Scratch rmware information register (lower byte)
Table 90.
Unlock Device register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
ULCODE[15:8] = AAh
Reset
not applicable
Bus reset
not applicable
Access
WWWWWWWW
Bit
7
6
5
4
3
2
1
0
Symbol
ULCODE[7:0] = 37h
Reset
not applicable
Bus reset
not applicable
Access
WWWWWWWW
Table 91.
Unlock Device register: bit description
Bit
Symbol
Description
15 to 0
ULCODE[15:0]
Unlock Code: Writing data AA37h unlocks internal registers and
FIFOs for writing, following a resume.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1583ET1-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET1TM | 制造商:STMicroelectronics 功能描述: |
| ISP1583ET2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller |
| ISP1583ET2,518 | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET2-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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