參數(shù)資料
型號(hào): ISP1583ET1,118
廠商: ST-ERICSSON
元件分類(lèi): 總線(xiàn)控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁(yè)數(shù): 56/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
58 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the rmware must not
reference the same endpoint on the Endpoint Index register.
9.4.9 DMA Strobe Timing register (address: 60h)
This 1-byte register controls the strobe timing for MDMA mode, when bits
DMA_MODE[1:0] in the DMA Conguration register have been set to 03h.
The bit allocation is given in Table 78.
[1]
The cycle duration indicates the internal clock cycle (33.3 ns/cycle).
Table 76.
DMA Endpoint register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
EPIDX[2:0]
DMADIR
Reset
----
0000
Bus reset
----
0000
Access
----
R/W
Table 77.
DMA Endpoint register: bit description
Bit
Symbol
Description
7 to 4
-
reserved
3 to 1
EPIDX[2:0]
Endpoint Index: selects the indicated endpoint for DMA access
0
DMADIR
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA read transfers
1 — Selects the TX/IN FIFO for DMA write transfers
Table 78.
DMA Strobe Timing register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
DMA_STROBE_CNT[4:0]
Reset
-
11111
Bus reset
-
11111
Access
-
R/W
Table 79.
DMA Strobe Timing register: bit description
Bit
Symbol
Description
7 to 5
-
reserved
4 to 0
DMA_STROBE_
CNT[4:0]
DMA Strobe Count: These bits select the strobe duration for
DMA_MODE = 03h (see Table 56). The strobe duration is (N + 1)
cycles[1], with N representing the value of DMA_STROBE_CNT (see
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