參數(shù)資料
型號: KM48S2020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動態(tài)RAM)
中文描述: 1M × 8位× 2銀行同步DRAM(1米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 23/44頁
文件大小: 605K
代理商: KM48S2020C
CMOS SDRAM
DEVICE OPERATIONS - I
ELECTRONICS
REV. 4 Feb. '98
*Note :
1. Active power down : one or both banks active state.
2. Precharge power down : both banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t
RFC
from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of t
auto refresh cycle (4096 cycles) is recommended.
RFC
from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst
10. Clock Suspend Exit & Power Down Exit
CLK
CKE
CMD
RD
1) Clock Suspend (=Active Power Down) Exit
tSS
CLK
CKE
CMD
2) Power Down (=Precharge Power Down)
Note 1
Note 5
Internal
CLK
NOP
tSS
Note 2
Internal
CLK
11. Auto Refresh & Self Refresh
CLK
CMD
1) Auto Refresh & Self Refresh
CKE
PRE
AR
CMD
Note 4
tRP
tRFC
ó
ó
ó
ó
CLK
CMD
2) Self Refresh
CKE
PRE
SR
CMD
Note 4
tRP
tRFC
ó
ó
Note 6
Note 3
ó
ACT
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