參數(shù)資料
型號: KM48S2020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動態(tài)RAM)
中文描述: 1M × 8位× 2銀行同步DRAM(1米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 31/44頁
文件大小: 605K
代理商: KM48S2020C
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Read & Write Cycle at Same Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(t
3. Access time from Row active command. t
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
SHZ
) after the clcok.
CC
*(t
RCD
+ CAS latency - 1) + t
SAC
Read
(A-Bank)
*Note 1
tRC
tRCD
*Note 2
tRDL
tRDL
tSHZ
*Note 4
tSHZ
*Note 4
tOH
tRAC
*Note 3
tSAC
tSAC
tRAC
*Note 3
tOH
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
Ra
Rb
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Ra
Ca0
Rb
Cb0
WE
DQM
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