參數(shù)資料
型號(hào): KM48S2020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 1M × 8位× 2銀行同步DRAM(1米× 8位× 2組同步動(dòng)態(tài)RAM)的
文件頁數(shù): 40/44頁
文件大小: 605K
代理商: KM48S2020C
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
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Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
Row Active
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
Write
(A-Bank)
*Note 2
tBDL
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
RDL.
HIGH
tRDL
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
RAa
CAa
CAb
RAa
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