參數(shù)資料
型號(hào)： KM48S2020C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動(dòng)態(tài)RAM)
中文描述： 1M × 8位× 2銀行同步DRAM（1米× 8位× 2組同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 43/44頁(yè)
文件大小： 605K
代理商： KM48S2020C
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
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Self Refresh Entry & Exit Cycle
Self Refresh Entry
: Don't care
*Note 1
*Note 7
ó
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Hi-Z
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Hi-Z
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Self Refresh Exit
Auto Refresh
tSS
*Note 2
*Note 3
*Note 4
tRCmin
*Note 6
*Note 5
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
*Note :
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays
cf.) Once the device enters self refresh mode, minimum t
"Low".
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst ref
resh.
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KM48S2020CT-G10 制造商:Samsung Semiconductor 功能描述:
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