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參數(shù)資料
| 型號： | KM48S2020C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動態(tài)RAM) |
| 中文描述： | 1M × 8位× 2銀行同步DRAM（1米× 8位× 2組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 27/44頁 |
| 文件大小： | 605K |
| 代理商： | KM48S2020C |
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CMOS SDRAM
DEVICE OPERATIONS - I
ELECTRONICS
REV. 4 Feb. '98
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
CS
RAS
CAS
WE
ADDR
ACTION
Note
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
OP Code
X
X
X
X
X
Self
Refresh
INVALID
Exit Self Refresh --> Idle after t
Exit Self Refresh --> Idle after t
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend
RFC
(ABI)
RFC
(ABI)
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
6
6
7
7
8
8
8
9
9
All
Banks
Idle
*Note :
6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + t
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
SS
must be satisfied before any command other than exit.
Abbreviations : ABI = All Banks Idle, RA = Row Address
CKE
(n-1)
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
CKE
n
All
Banks
Precharge
Power
Down
Any State
other than
Listed
above
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相關代理商/技術參數(shù) |
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| KM48S2020CT-G10 | 制造商:Samsung Semiconductor 功能描述: |
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| KM48S8030C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit x 4 Banks Synchronous DRAM |
| KM48S8030CT-G/FA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit x 4 Banks Synchronous DRAM |
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