參數(shù)資料
型號: KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 43/43頁
文件大?。?/td> 604K
代理商: KM48S8020B
ELECTRONICS
REV. 2 Mar. '98
TIMING DIAGRAM - II
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Mode Register Set Cycle
HIGH
MRS
Auto Refresh
: Don't care
*Note :
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
New
Command
New Command
Hi-Z
Hi-Z
tRFC
HIGH
MODE REGISTER SET CYCLE
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
Auto Refresh Cycle
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Key
Ra
*Note 3
*Note 1
*Note 2
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
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