參數資料
型號: KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動態(tài)RAM)的
文件頁數: 28/43頁
文件大?。?/td> 604K
代理商: KM48S8020B
ELECTRONICS
REV. 2 Mar. '98
TIMING DIAGRAM - II
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
*Note :
1. All inputs expect CKE & DQM can be don
t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
BA
0
1
0
1
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
4. A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP
BA
0
1
Active & Read/Write
Bank A
Bank B
BA
0
1
X
Precharge
Bank A
Bank B
Both Banks
A10/AP
0
0
1
0
1
相關PDF資料
PDF描述
KM48S8030D 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
KM48S8030 2M x 8Bit x 4 Banks Synchronous DRAM
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KM48V2004C 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動態(tài)RAM(帶擴展數據輸出))
KM48C2004C 2M x 8Bit CMOS Dynamic RAM with Extended Data Out(2M x 8位CMOS 動態(tài)RAM(帶擴展數據輸出))
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