參數(shù)資料
型號: KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 34/43頁
文件大?。?/td> 604K
代理商: KM48S8020B
ELECTRONICS
REV. 2 Mar. '98
TIMING DIAGRAM - II
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Read & Write Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Write
(B-Bank)
Row Active
(A-Bank)
: Don't care
*Note :
1. t
CDL
should be met to complete write.
Read
(A-Bank)
*Note 1
tCDL
Row Active
(B-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0
QAa1
QAa2
QAa3
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
QAc2
QAc0
QAc1
RAa
CAa
RBb
CBb
RAc
CAc
RAc
RAa
RBb
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