參數(shù)資料
型號: KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 29/43頁
文件大?。?/td> 604K
代理商: KM48S8020B
ELECTRONICS
REV. 2 Mar. '98
TIMING DIAGRAM - II
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Power Up Sequence
: Don't care
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
A
10
/AP
DQ
WE
DQM
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
RAa
RAa
tRP
tRFC
High level is necessary
High-Z
High level is necessary
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
ó
tRFC
Key
相關(guān)PDF資料
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