參數(shù)資料
型號(hào): KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 21/43頁(yè)
文件大?。?/td> 604K
代理商: KM48S8020B
CMOS SDRAM
DEVICE OPERATIONS - II
ELECTRONICS
REV. 3 Feb. '98
*Note :
1. t
RDL
: 1 CLK
2. t
BDL
: 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at both banks precharge state.
8. Burst Stop & Interrupted by Precharge
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
PRE
Q
0
Q
1
Q
0
Q
1
1
2
9. MRS
CLK
PRE
1) Mode Register Set
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
STOP
Q
0
Q
1
Q
0
Q
1
1
2
MRS
ACT
Note 4
tRP
2CLK
CMD
D
0
D
1
D
2
CLK
CMD
DQ
WR
PRE
D
3
1) Normal Write (BL=4)
tRDL Note 1
D
0
D
1
D
2
CLK
CMD
DQ
WR
STOP
D
3
2) Write Burst Stop (BL=8)
DQM
DQM
tBDL Note 2
D
4
D
5
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