參數(shù)資料
型號(hào): KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 18/43頁(yè)
文件大?。?/td> 604K
代理商: KM48S8020B
CMOS SDRAM
DEVICE OPERATIONS - II
ELECTRONICS
REV. 3 Feb. '98
1) Read interrupted by Read (BL=4)
3. CAS Interrupt (I)
CLK
CMD
ADD
Note 1
RD
RD
A
B
QA
0
QB
1
QB
2
QB
3
QB
0
QA
0
QB
1
QB
2
QB
3
QB
0
tCCD
Note 2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
WR
WR
A
B
tCCD Note 2
DA
0
DB
1
DB
0
tCDL
Note 3
CLK
CMD
ADD
DQ
WR
RD
A
B
tCCD Note 2
tCDL
Note 3
DA
0
QB
1
QB
0
DA
0
QB
1
QB
0
DQ(CL2)
DQ(CL3)
*Note :
1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. t
CCD
: CAS to CAS delay. (=1CLK)
3. t
CDL
: Last data in to new column address delay. (=1CLK)
DQ(CL2)
DQ(CL3)
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