參數(shù)資料
型號(hào)： KMC8610VT1333JB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/96頁(yè)
文件大?。?/td> 0K
描述： IC HOST PROCESS 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19
2.2
Power Sequencing
The MPC8610 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows:
The chronological order of power up is:
1.
OVDD, BVDD
2.
VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD (this rail must reach
90% of its value before the rail for GVDD and MVREF reaches 10% of its value)
3.
GVDD, MVREF
4.
SYSCLK
The order of power down is as follows:
1.
SYSCLK
2.
GVDD, MVREF
3.
VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD
4.
ODD, BVDD
NOTE
AVDD type supplies should be delayed with respect to their source supplies by the RC time
constant of the PLL filter circuit described in Section 3.2, “Power Supply Design and
Local bus
25
35
BVDD = 3.3 V
BVDD = 2.5 V
2
45 (default)
125
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
PCI, DUART, DMA, interrupts, system control and clocking, debug,
test, JTAG, power management, and miscellaneous I/O voltage
45
OVDD = 3.3 V
I2C
150
OVDD = 3.3 V
PCI Express
100
XVDD = 1.0 V
3
Notes:
1. See the DDR control driver registers in the
MPC8610 Integrated Host Processor Reference Manual, for more information.
2. See the POR impedance control register in the
MPC8610 Integrated Host Processor Reference Manual, for more information
about local bus signals and their drive strength programmability.
3. See Section 1, “Pin Assignments and Reset States,” for details on resistor requirements for the calibration of
SD
n_IMP_CAL_TX and SDn_IMP_CAL_RX transmit and receive signals.
4. Stub series terminated logic (SSTL-25) type pins.
5. Stub series terminated logic (SSTL-18) type pins.
6. The drive strength of the DDR interface in half strength mode is at Tj = 105°C and at GVDD (min).
Table 4. Output Drive Capability (continued)
Driver Type
Programmable
Output Impedance
(
Ω)
Supply
Voltage
Notes
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