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| 型號： | KMC8610VT1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 87/96頁 |
| 文件大小： | 0K |
| 描述： | IC HOST PROCESS 1333MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Hardware Design Considerations
Freescale Semiconductor
88
Thermagon Inc.
888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
3.12.2.3
Heat Sink Selection Example
This section provides a heat sink selection example using one of the commercially available heat sinks.
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = Ti + Tr + (RθJC + Rθint + Rθsa) × Pd
where:
Tj is the die-junction temperature
Ti is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
RθJC is the junction-to-case thermal resistance
Rθint is the adhesive or interface material thermal resistance
Rθsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3. The
temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise
within the electronic cabinet. An electronic cabinet inlet-air temperature (Ti) may range from 30° to 40°C. The air temperature
rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material (Rθint) is
typically about 0.2
°C/W. For example, assuming a Ti of 30°C, a Tr of 5°C, a package RθJC = 0.1, and a typical power
consumption (Pd) of 10 W, the following expression for Tj is obtained:
Die-junction temperature:
Tj = 30°C + 5°C + (0.1°C/W + 0.2°C/W + θsa) × 10 W
For this example, a Rθsavalue of 6.7°C/W or less is required to maintain the die junction temperature below the maximum value
of Table 3.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for
comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only
using this metric in determining thermal management because no single parameter can adequately describe three-dimensional
heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect
the final operating die-junction temperature—airflow, board population (local heat flux of adjacent components), heat sink
efficiency, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on.
Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined
effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we
recommend using conjugate heat transfer models for the board as well as system-level designs.
3.12.2.4
Recommended Thermal Model
For system thermal modeling, the MPC8610 thermal model is shown in Figure 57. Four cuboids are used to represent this
device. The die is modeled as 8.5 × 9.7 mm at a thickness of 0.86 mm. See Section 2.3, “Power Characteristics,” for power
dissipation details. The substrate is modeled as a single block 29 × 29 × 1.18 mm with orthotropic conductivity of
23.3 W/(m K) in the xy-plane and 0.95 W/(m K) in the z-direction. The die is centered on the substrate. The bump/underfill
layer is modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 8.1 W/(m K) in the
thickness dimension of 0.07 mm. The C5 solder layer is modeled as a cuboid with dimensions 29 × 29 × 0.4 mm with orthotropic
thermal conductivity of 0.034 W/(m K) in the xy-plane and 12.1 W/(m K) in the z-direction. An LGA solder layer would be
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