參數(shù)資料
型號(hào)： KMC8610VT1333JB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 50/96頁(yè)
文件大?。?/td> 0K
描述： IC HOST PROCESS 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
54
Figure 28 shows the PCI output AC timing conditions.
Figure 28. PCI Output AC Timing Measurement Condition
2.17
High-Speed Serial Interfaces (HSSI)
The MPC8610 features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect
applications. The SerDes1 interface is dedicated for PCI Express (x1/x2/x4) data transfers. The SerDes2 interface is dedicated
for PCI Express (x1/x2/x4/x8) data transfers.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.17.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Figure 29 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure
shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each
signal swings between A volts and B volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
1.
Single-ended swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX, and SDn_RX each have a
peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing.
2.
Differential output voltage, VOD (or differential output swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary
output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive or negative.
3.
Differential input voltage, VID (or differential input swing):
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary
input voltages: VSDn_RX –VSDn_RX. The VID value can be either positive or negative.
4.
Differential peak voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as
differential peak voltage, VDIFFp = |A – B| volts.
5.
Differential peak-to-peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from
A – B to -(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver
input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 * VDIFFp = 2 * |(A – B)| volts, which is twice
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output
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